1. Field of the Invention.
The field of the invention is that of bus architectures for electronic digital information storage, comprising an addressing and retrieval apparatus thereof. Specifically, the present invention is a bus architecture for an array of memory devices.
2. Prior Art.
Computer memories are typically addressed in a linear addressing mode. In linear addressing each memory element is referred to by a unique number. This is sometimes referred to as a linear array. Each memory address typically referenced some n number of bits-originally n being 8 bits or 1 byte, later 16-bits or one word, or even 32-bits which is referred to as a word or a long word. A bus connects the memories with a processor. The processor accesses memory by supplying an address to a bus controller, which fetches the desired data.
For graphics applications, a variation is made upon the linear array. This variation is often referred to as bit mapped graphics. Each atomic position in the graphical display is called a "pixel," and each pixel has a unique address. A piece of pixel data can be any length ranging from one bit to sixteen bits to any finite number. A one bit pixel typically indicates light or dark on the display. A three or four bit pixel typically represents a color for the corresponding position on the display.
In bit map graphics the addressing space is referred to by row and column indexes. A typical CRT display is a 640 pixel by 400 pixel array, with a black and white pixel being represented as one bit and a color pixel as three bits. Under these methods the individual memory locations are referenced by their position on the X Y coordinate grid. However, the implementation of the (X, Y) coordinate is a simple linear combination to produce the actual linear address. By being constrained to such linear addressing modes, many graphical operations proved to be quite time consuming and difficult.
For example, reading row or column vectors is a common graphical operation. It is often the case that multiple accesses are needed as well as complicated sorting algorithms after the fetching of the data. With a 640.times.400 array of bytes where one byte equals one pixel, a 32-bit bus accesses a vector comprising four contiguous bytes in one fetch. Depending on the organization of the arrays that either allowed for quick retrieval of a 4 byte row or column vector. However, it would take four fetches to obtain a 4 byte vector of the other dimension, as well as extra calculation to determine the physical addresses.
With a 640.times.400 pixel array, there are 256,000 pixels that must be updated in 0.1 seconds or less. It is expedient to modify as many pixels as possible in one bus cycle. In fact, with a typical 480 ns bus cycle time it is not possible to modify that many pixels in 0.1 seconds if one pixel at a time. Therefore, as many pixels as can fit on a bus cycle are typically character display processed at once.
Regardless of the streamlining and optimization involved, in order to get one bus vector of data it is still necessary for multiple fetches in the case of nonaligned data. For example, if a computer with a 16-bit bus addressed its memory on 16-bit boundary lines but had 8-bit pixels, two fetches are required to retrieve a two pixel vector that lay across boundary lines. That is, the first pixel is the least significant byte of the lower address and the second pixel is the most significant byte of the higher address. The first fetch retrieves one address and stores the relevant pixel, then the second fetch retrieves the other address and stores the relevant pixel.
The prior art methods of addressing generally are limited to horizontal vectors and none took optimum advantage of the fast pagemode of DRAMs. With only horizontal vectors being accessible, a multiple number of accesses are needed to produce column vectors along with much complicated processing of the information retrieved thereof.
In graphics processing it is common to process small rectangular areas, since these correspond to characters. However, where there are non-aligned boundaries of the rectangular areas and the size of the rectangles does not fit exactly with the linear address arrays, then problems are further compounded. The multiple fetches necessary, to access a vertical vector, are multiplied by the additional dimension of the region.
An example of a Prior Art DRAM Array is described in U.S. Pat. No. 4,038,646, which is assigned to the assignee of the present invention.
What is lacking is a device that could take advantage of the properties of DRAMs which consist of the ability for fast access along columns as well as rows. One object of the present invention is to provide for a device which can fully utilize the efficient properties of CMOS DRAMs and other such logical memory devices. Another object of the invention is to provide for higher dimensional arrays which will allow for access of vectors along any dimension with equal ease.